S912XEG128W1MAA NXP
| Available |
S912XEG128W1MAA NXP
• Paging capability to support a global 8 Mbytes memory address space
• Bus arbitration between the masters CPU, BDM and XGATE
• Simultaneous accesses to different resources1 (internal, external, and peripherals) (see Figure 3-1 )
• Resolution of target bus access collision
• MCU operation mode control
• MCU security control
• Separate memory map schemes for each master CPU, BDM and XGATE
• ROM control bits to enable the on-chip FLASH or ROM selection
• Port replacement registers access control
• Generation of system reset when CPU accesses an unimplemented address (i.e., an address which does not belong to any of the on-chip modules) in single-chip modes
• Paging capability to support a global 8 Mbytes memory address space
• Bus arbitration between the masters CPU, BDM and XGATE
• Simultaneous accesses to different resources1 (internal, external, and peripherals) (see Figure 3-1 )
• Resolution of target bus access collision
• MCU operation mode control
• MCU security control
• Separate memory map schemes for each master CPU, BDM and XGATE
• ROM control bits to enable the on-chip FLASH or ROM selection
• Port replacement registers access control
• Generation of system reset when CPU accesses an unimplemented address (i.e., an address which does not belong to any of the on-chip modules) in single-chip modes
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