SPC5746CSK1AMKU6 NXP
Available
SPC5746CSK1AMKU6 NXP
• 1 × 160 MHz Power Architecture® e200z4 Dual issue, 32-bit CPU – Single precision floating point operations – 8 KB instruction cache and 4 KB data cache – Variable length encoding (VLE) for significant code density improvements • 1 x 80 MHz Power Architecture® e200z2 Single issue, 32-bit CPU – Using variable length encoding (VLE) for significant code size footprint reduction • End to end ECC – All bus masters, for example, cores, generate a single error correction, double error detection (SECDED) code for every bus transaction – SECDED covers 64-bit data and 29-bit address • Memory interfaces – 3 MB on-chip flash memory supported with the flash memory controller – 3 x flash memory page buffers (3-port flash memory controller) – 384 KB on-chip SRAM across three RAM ports • Clock interfaces – 8-40 MHz external crystal (FXOSC) – 16 MHz IRC (FIRC) – 128 KHz IRC (SIRC) – 32 KHz external crystal (SXOSC) – Clock Monitor Unit (CMU) – Frequency modulated phase-locked loop (FMPLL) – Real Time Counter (RTC) • System Memory Protection Unit (SMPU) with up to 32 region descriptors and 16-byte region granularity • 16 Semaphores to manage access to shared resources • Interrupt controller (INTC) capable of routing interrupts to any CPU • Crossbar switch architecture for concurrent access to peripherals, flash memory, and RAM from multiple bus masters
• 1 × 160 MHz Power Architecture® e200z4 Dual issue, 32-bit CPU – Single precision floating point operations – 8 KB instruction cache and 4 KB data cache – Variable length encoding (VLE) for significant code density improvements • 1 x 80 MHz Power Architecture® e200z2 Single issue, 32-bit CPU – Using variable length encoding (VLE) for significant code size footprint reduction • End to end ECC – All bus masters, for example, cores, generate a single error correction, double error detection (SECDED) code for every bus transaction – SECDED covers 64-bit data and 29-bit address • Memory interfaces – 3 MB on-chip flash memory supported with the flash memory controller – 3 x flash memory page buffers (3-port flash memory controller) – 384 KB on-chip SRAM across three RAM ports • Clock interfaces – 8-40 MHz external crystal (FXOSC) – 16 MHz IRC (FIRC) – 128 KHz IRC (SIRC) – 32 KHz external crystal (SXOSC) – Clock Monitor Unit (CMU) – Frequency modulated phase-locked loop (FMPLL) – Real Time Counter (RTC) • System Memory Protection Unit (SMPU) with up to 32 region descriptors and 16-byte region granularity • 16 Semaphores to manage access to shared resources • Interrupt controller (INTC) capable of routing interrupts to any CPU • Crossbar switch architecture for concurrent access to peripherals, flash memory, and RAM from multiple bus masters
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