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MCIMX6Q6AVT08AE NXP
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MCIMX6Q6AVT08AE NXP
The i.MX 6Dual/6Quad processors are based on Arm Cortex-A9 MPCore platform, which has the following features: • Arm Cortex-A9 MPCore 4xCPU processor (with TrustZone®) • The core configuration is symmetric, where each core includes: — 32 KByte L1 Instruction Cache — 32 KByte L1 Data Cache — Private Timer and Watchdog — Cortex-A9 NEON MPE (Media Processing Engine) Co-processor The Arm Cortex-A9 MPCore complex includes: • General Interrupt Controller (GIC) with 128 interrupt support • Global Timer • Snoop Control Unit (SCU) • 1 MB unified I/D L2 cache, shared by two/four cores • Two Master AXI (64-bit) bus interfaces output of L2 cache Part differentiator @ Industrial with VPU, GPU, no MLB 7 Automotive with VPU, GPU 6 Consumer with VPU, GPU 5 Automotive with GPU, no VPU 4 Temperature Tj + Extended commercial: -20 to +105° C E Industrial: -40 to +105° C C Automotive: -40 to +125° C A Frequency $$ 800 MHz2 (Industrial grade) 08 852 MHz (Automotive grade) 08 1 GHz3 10 1.2 GHz 12 Package type RoHS FCPBGA 21x21 0.8mm (lidded) VT FCPBGA 21x21 0.8mm (non lidded) YM Qualification level MC Prototype Samples PC Mass Production MC Special SC Part # series X i.MX 6Quad Q i.MX 6Dual D Silicon revision1 A Rev 1.2 C Rev 1.3 D Rev 1.6 E Fusing % Default setting A HDCP enabled C MC IMX6 X @ + VV $$ % A 1. See the nxp.com\imx6series Web page for latest information on the available silicon revision. 2. If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 792 MHz. 3. If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 996 MHz. i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 6, 11/2018 6 NXP Semiconductors Introduction • Frequency of the core (including Neon and L1 cache) as per Table 6. • NEON MPE coprocessor — SIMD Media Processing Architecture — NEON register file with 32x64-bit general-purpose registers — NEON Integer execute pipeline (ALU, Shift, MAC) — NEON dual, single-precision floating point execute pipeline (FADD, FMUL) — NEON load/store and permute pipeline The SoC-level memory system consists of the following additional components: • Boot ROM, including HAB (96 KB) • Internal multimedia / shared, fast access RAM (OCRAM, 256 KB) • Secure/non-secure RAM (16 KB) • External memory interfaces: — 16-bit, 32-bit, and 64-bit DDR3-1066, DDR3L-1066, and 1/2 LPDDR2-800 channels, supporting DDR interleaving mode, for dual x32 LPDDR2 — 8-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size, BA-NAND, PBA-NAND, LBA-NAND, OneNAND™ and others. BCH ECC up to 40 bit. — 16/32-bit NOR Flash. All EIMv2 pins are muxed on other interfaces. — 16/32-bit PSRAM, Cellular RAM Each i.MX 6Dual/6Quad processor enables the following interfaces to external devices (some of them are muxed and not available simultaneously): • Hard Disk Drives—SATA II, 3.0 Gbps • Displays—Total five interfaces available. Total raw pixel rate of all interfaces is up to 450 Mpixels/sec, 24 bpp. Up to four interfaces may be active in parallel. — One Parallel 24-bit display port, up to 225 Mpixels/sec (for example, WUXGA at 60 Hz or dual HD1080 and WXGA at 60 Hz) — LVDS serial ports—One port up to 170 Mpixels/sec (for example, WUXGA at 60 Hz) or two ports up to 85 MP/sec each — HDMI 1.4 port — MIPI/DSI, two lanes at 1 Gbps • Camera sensors: — Parallel Camera port (up to 20 bit and up to 240 MHz peak) — MIPI CSI-2 serial camera port, supporting up to 1000 Mbps/lane in 1/2/3-lane mode and up to 800 Mbps/lane in 4-lane mode. The CSI-2 Receiver core can manage one clock lane and up to four data lanes. Each i.MX 6Dual/6Quad processor has four lanes. • Expansion cards: — Four MMC/SD/SDIO card ports all supporting: – 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to UHS-I SDR-104 mode (104 MB/s max) Introduction i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 6, 11/2018 NXP Semiconductors 7 – 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52 MHz in both SDR and DDR modes (104 MB/s max) • USB: — One High Speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB PHY — Three USB 2.0 (480 Mbps) hosts: – One HS host with integrated High Speed PHY – Two HS hosts with integrated High Speed Inter-Chip (HS-IC) USB PHY • Expansion PCI Express port (PCIe) v2.0 one lane — PCI Express (Gen 2.0) dual mode complex, supporting Root complex operations and Endpoint operations. Uses x1 PHY configuration. • Miscellaneous IPs and interfaces: — SSI block capable of supporting audio sample frequencies up to 192 kHz stereo inputs and outputs with I2 S mode — ESAI is capable of supporting audio sample frequencies up to 260 kHz in I2S mode with 7.1 multi channel outputs — Five UARTs, up to 5.0 Mbps each: – Providing RS232 interface – Supporting 9-bit RS485 multidrop mode – One of the five UARTs (UART1) supports 8-wire while the other four support 4-wire. This is due to the SoC IOMUX limitation, because all UART IPs are identical. — Five eCSPI (Enhanced CSPI) — Three I2C, supporting 400 kbps — Gigabit Ethernet Controller (IEEE1588 compliant), 10/100/10001 Mbps — Four Pulse Width Modulators (PWM) — System JTAG Controller (SJC) — GPIO with interrupt capabilities — 8x8 Key Pad Port (KPP) — Sony Philips Digital Interconnect Format (SPDIF), Rx and Tx — Two Controller Area Network (FlexCAN), 1 Mbps each — Two Watchdog timers (WDOG) — Audio MUX (AUDMUX) — MLB (MediaLB) provides interface to MOST Networks (150 Mbps) with the option of DTCP cipher accelerator The i.MX 6Dual/6Quad processors integrate advanced power management unit and controllers: • Provide PMU, including LDO supplies, for on-chip resources • Use Temperature Sensor for monitoring the die temperature 1. The theoretical maximum performance of 1 Gbps ENET is limited to 470 Mbps (total for Tx and Rx) due to internal bus throughput limitations. The actual measured performance in optimized environment is up to 400 Mbps. For details, see the ERR004512 erratum in the i.MX 6Dual/6Quad errata document (IMX6DQCE). i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 6, 11/2018 8 NXP Semiconductors Introduction • Support DVFS techniques for low power modes • Use Software State Retention and Power Gating for Arm and MPE • Support various levels of system power modes • Use flexible clock gating control scheme The i.MX 6Dual/6Quad processors use dedicated hardware accelerators to meet the targeted multimedia performance. The use of hardware accelerators is a key factor in obtaining high performance at low power consumption numbers, while having the CPU core relatively free for performing other tasks. The i.MX 6Dual/6Quad processors incorporate the following hardware accelerators: • VPU—Video Processing Unit • IPUv3H—Image Processing Unit version 3H (2 IPUs) • GPU3Dv4—3D Graphics Processing Unit (OpenGL ES 2.0) version 4 • GPU2Dv2—2D Graphics Processing Unit (BitBlt) version 2 • GPUVG—OpenVG 1.1 Graphics Processing Unit • ASRC—Asynchronous Sample Rate Converter Security functions are enabled and accelerated by the following hardware: • Arm TrustZone including the TZ architecture (separation of interrupts, memory mapping, etc.) • SJC—System JTAG Controller. Protecting JTAG from debug port attacks by regulating or blocking the access to the system debug features. • CAAM—Cryptographic Acceleration and Assurance Module, containing 16 KB secure RAM and True and Pseudo Random Number Generator (NIST certified) • SNVS—Secure Non-Volatile Storage, including Secure Real Time Clock • CSU—Central Security Unit. Enhancement for the IC Identification Module (IIM). Will be configured during boot and by eFUSEs and will determine the security level operation mode as well as the TZ policy. • A-HAB—Advanced High Assurance Boot—HABv4 with the new embedded enhancements: SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization.
The i.MX 6Dual/6Quad processors are based on Arm Cortex-A9 MPCore platform, which has the following features: • Arm Cortex-A9 MPCore 4xCPU processor (with TrustZone®) • The core configuration is symmetric, where each core includes: — 32 KByte L1 Instruction Cache — 32 KByte L1 Data Cache — Private Timer and Watchdog — Cortex-A9 NEON MPE (Media Processing Engine) Co-processor The Arm Cortex-A9 MPCore complex includes: • General Interrupt Controller (GIC) with 128 interrupt support • Global Timer • Snoop Control Unit (SCU) • 1 MB unified I/D L2 cache, shared by two/four cores • Two Master AXI (64-bit) bus interfaces output of L2 cache Part differentiator @ Industrial with VPU, GPU, no MLB 7 Automotive with VPU, GPU 6 Consumer with VPU, GPU 5 Automotive with GPU, no VPU 4 Temperature Tj + Extended commercial: -20 to +105° C E Industrial: -40 to +105° C C Automotive: -40 to +125° C A Frequency $$ 800 MHz2 (Industrial grade) 08 852 MHz (Automotive grade) 08 1 GHz3 10 1.2 GHz 12 Package type RoHS FCPBGA 21x21 0.8mm (lidded) VT FCPBGA 21x21 0.8mm (non lidded) YM Qualification level MC Prototype Samples PC Mass Production MC Special SC Part # series X i.MX 6Quad Q i.MX 6Dual D Silicon revision1 A Rev 1.2 C Rev 1.3 D Rev 1.6 E Fusing % Default setting A HDCP enabled C MC IMX6 X @ + VV $$ % A 1. See the nxp.com\imx6series Web page for latest information on the available silicon revision. 2. If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 792 MHz. 3. If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 996 MHz. i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 6, 11/2018 6 NXP Semiconductors Introduction • Frequency of the core (including Neon and L1 cache) as per Table 6. • NEON MPE coprocessor — SIMD Media Processing Architecture — NEON register file with 32x64-bit general-purpose registers — NEON Integer execute pipeline (ALU, Shift, MAC) — NEON dual, single-precision floating point execute pipeline (FADD, FMUL) — NEON load/store and permute pipeline The SoC-level memory system consists of the following additional components: • Boot ROM, including HAB (96 KB) • Internal multimedia / shared, fast access RAM (OCRAM, 256 KB) • Secure/non-secure RAM (16 KB) • External memory interfaces: — 16-bit, 32-bit, and 64-bit DDR3-1066, DDR3L-1066, and 1/2 LPDDR2-800 channels, supporting DDR interleaving mode, for dual x32 LPDDR2 — 8-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size, BA-NAND, PBA-NAND, LBA-NAND, OneNAND™ and others. BCH ECC up to 40 bit. — 16/32-bit NOR Flash. All EIMv2 pins are muxed on other interfaces. — 16/32-bit PSRAM, Cellular RAM Each i.MX 6Dual/6Quad processor enables the following interfaces to external devices (some of them are muxed and not available simultaneously): • Hard Disk Drives—SATA II, 3.0 Gbps • Displays—Total five interfaces available. Total raw pixel rate of all interfaces is up to 450 Mpixels/sec, 24 bpp. Up to four interfaces may be active in parallel. — One Parallel 24-bit display port, up to 225 Mpixels/sec (for example, WUXGA at 60 Hz or dual HD1080 and WXGA at 60 Hz) — LVDS serial ports—One port up to 170 Mpixels/sec (for example, WUXGA at 60 Hz) or two ports up to 85 MP/sec each — HDMI 1.4 port — MIPI/DSI, two lanes at 1 Gbps • Camera sensors: — Parallel Camera port (up to 20 bit and up to 240 MHz peak) — MIPI CSI-2 serial camera port, supporting up to 1000 Mbps/lane in 1/2/3-lane mode and up to 800 Mbps/lane in 4-lane mode. The CSI-2 Receiver core can manage one clock lane and up to four data lanes. Each i.MX 6Dual/6Quad processor has four lanes. • Expansion cards: — Four MMC/SD/SDIO card ports all supporting: – 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to UHS-I SDR-104 mode (104 MB/s max) Introduction i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 6, 11/2018 NXP Semiconductors 7 – 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52 MHz in both SDR and DDR modes (104 MB/s max) • USB: — One High Speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB PHY — Three USB 2.0 (480 Mbps) hosts: – One HS host with integrated High Speed PHY – Two HS hosts with integrated High Speed Inter-Chip (HS-IC) USB PHY • Expansion PCI Express port (PCIe) v2.0 one lane — PCI Express (Gen 2.0) dual mode complex, supporting Root complex operations and Endpoint operations. Uses x1 PHY configuration. • Miscellaneous IPs and interfaces: — SSI block capable of supporting audio sample frequencies up to 192 kHz stereo inputs and outputs with I2 S mode — ESAI is capable of supporting audio sample frequencies up to 260 kHz in I2S mode with 7.1 multi channel outputs — Five UARTs, up to 5.0 Mbps each: – Providing RS232 interface – Supporting 9-bit RS485 multidrop mode – One of the five UARTs (UART1) supports 8-wire while the other four support 4-wire. This is due to the SoC IOMUX limitation, because all UART IPs are identical. — Five eCSPI (Enhanced CSPI) — Three I2C, supporting 400 kbps — Gigabit Ethernet Controller (IEEE1588 compliant), 10/100/10001 Mbps — Four Pulse Width Modulators (PWM) — System JTAG Controller (SJC) — GPIO with interrupt capabilities — 8x8 Key Pad Port (KPP) — Sony Philips Digital Interconnect Format (SPDIF), Rx and Tx — Two Controller Area Network (FlexCAN), 1 Mbps each — Two Watchdog timers (WDOG) — Audio MUX (AUDMUX) — MLB (MediaLB) provides interface to MOST Networks (150 Mbps) with the option of DTCP cipher accelerator The i.MX 6Dual/6Quad processors integrate advanced power management unit and controllers: • Provide PMU, including LDO supplies, for on-chip resources • Use Temperature Sensor for monitoring the die temperature 1. The theoretical maximum performance of 1 Gbps ENET is limited to 470 Mbps (total for Tx and Rx) due to internal bus throughput limitations. The actual measured performance in optimized environment is up to 400 Mbps. For details, see the ERR004512 erratum in the i.MX 6Dual/6Quad errata document (IMX6DQCE). i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 6, 11/2018 8 NXP Semiconductors Introduction • Support DVFS techniques for low power modes • Use Software State Retention and Power Gating for Arm and MPE • Support various levels of system power modes • Use flexible clock gating control scheme The i.MX 6Dual/6Quad processors use dedicated hardware accelerators to meet the targeted multimedia performance. The use of hardware accelerators is a key factor in obtaining high performance at low power consumption numbers, while having the CPU core relatively free for performing other tasks. The i.MX 6Dual/6Quad processors incorporate the following hardware accelerators: • VPU—Video Processing Unit • IPUv3H—Image Processing Unit version 3H (2 IPUs) • GPU3Dv4—3D Graphics Processing Unit (OpenGL ES 2.0) version 4 • GPU2Dv2—2D Graphics Processing Unit (BitBlt) version 2 • GPUVG—OpenVG 1.1 Graphics Processing Unit • ASRC—Asynchronous Sample Rate Converter Security functions are enabled and accelerated by the following hardware: • Arm TrustZone including the TZ architecture (separation of interrupts, memory mapping, etc.) • SJC—System JTAG Controller. Protecting JTAG from debug port attacks by regulating or blocking the access to the system debug features. • CAAM—Cryptographic Acceleration and Assurance Module, containing 16 KB secure RAM and True and Pseudo Random Number Generator (NIST certified) • SNVS—Secure Non-Volatile Storage, including Secure Real Time Clock • CSU—Central Security Unit. Enhancement for the IC Identification Module (IIM). Will be configured during boot and by eFUSEs and will determine the security level operation mode as well as the TZ policy. • A-HAB—Advanced High Assurance Boot—HABv4 with the new embedded enhancements: SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization.
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