• 16-Bit CPU12X — Upward compatible with MC9S12 instruction set with the exception of five Fuzzy instructions (MEM, WAV, WAVR, REV, REVW) which have been removed — Enhanced indexed addressing — Access to large data segments independent of PPAGE • INT (interrupt module) — Eight levels of nested interrupts — Flexible assignment of interrupt sources to each interrupt level. — External non-maskable high priority interrupt (XIRQ) — Internal non-maskable high priority Memory Protection Unit interrupt — Up to 24 pins on ports J, H and P configurable as rising or falling edge sensitive interrupts • EBI (external bus interface)(available in 208-Pin and 144-Pin packages only) — Up to four chip select outputs to select 16K, 1M, 2M and up to 4MByte address spaces — Each chip select output can be configured to complete transaction on either the time-out of one of the two wait state generators or the deassertion of EWAIT signal • MMC (module mapping control) • DBG (debug module) — Monitoring of CPU and/or XGATE busses with tag-type or force-type breakpoint requests — 64 x 64-bit circular trace buffer captures change-of-flow or memory access information • BDM (background debug mode) • MPU (memory protection unit) — 8 address regions definable per active program task — Address range granularity as low as 8-bytes — No write / No execute Protection Attributes — Non-maskable interrupt on access violation • XGATE — Programmable, high performance I/O coprocessor module — Transfers data to or from all peripherals and RAM without CPU intervention or CPU wait states — Performs logical, shifts, arithmetic, and bit operations on data — Can interrupt the HCS12X CPU signalling transfer completion — Triggers from any hardware module as well as from the CPU possible — Two interrupt levels to service high priority tasks — Hardware support for stack pointer initialisation • OSC_LCP (oscillator) — Low power loop control Pierce oscillator utilizing a 4MHz to 16MHz crystal — Good noise immunity — Full-swing Pierce option utilizing a 2MHz to 40MHz crystal — Transconductance sized for optimum start-up margin for typical crystals • IPLL (Internally filtered, frequency modulated phase-locked-loop clock generation)
— No external components required — Configurable option to spread spectrum for reduced EMC radiation (frequency modulation) • CRG (clock and reset generation) — COP watchdog — Real time interrupt — Clock monitor — Fast wake up from STOP in self clock mode • Memory Options — 128K, 256k, 384K, 512K, 768K and 1M byte Flash — 2K, 4K byte emulated EEPROM — 12K, 16K, 24K, 32K, 48K and 64K Byte RAM • Flash General Features — 64 data bits plus 8 syndrome ECC (Error Correction Code) bits allow single bit failure correction and double fault detection — Erase sector size 1024 bytes — Automated program and erase algorithm • D-Flash Features — Up to 32 Kbytes of D-Flash memory with 256 byte sectors for user access. — Dedicated commands to control access to the D-Flash memory over EEE operation. — Single bit fault correction and double bit fault detection within a word during read operations. — Automated program and erase algorithm with verify and generation of ECC parity bits. — Fast sector erase and word program operation. — Ability to program up to four words in a burst sequence • Emulated EEPROM Features — Automatic EEE file handling using an internal Memory Controller. — Automatic transfer of valid EEE data from D-Flash memory to buffer RAM on reset. — Ability to monitor the number of outstanding EEE related buffer RAM words left to be programmed into D-Flash memory. — Ability to disable EEE operation and allow priority access to the D-Flash memory. — Ability to cancel all pending EEE operations and allow priority access to the D-Flash memory. • Two 16-channel, 12-bit Analog-to-Digital Converters — 8/10/12 Bit resolution — 3µs, 10-bit single conversion time — Left/right, signed/unsigned result data — External and internal conversion trigger capability — Internal oscillator for conversion in Stop modes — Wake from low power modes on analog comparison > or <= match • Five MSCAN (1 M bit per second, CAN 2.0 A, B software compatible modules) — Five receive and three transmit buffers
— Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit, or 8 x 8 bit — Four separate interrupt channels for Rx, Tx, error, and wake-up — Low-pass filter wake-up function — Loop-back for self-test operation • ECT (enhanced capture timer) — 8 x 16-bit channels for input capture or output compare — 16-bit free-running counter with 8-bit precision prescaler — 16-bit modulus down counter with 8-bit precision prescaler — Four 8-bit or two 16-bit pulse accumulators • TIM (standard timer module) — 8 x 16-bit channels for input capture or output compare — 16-bit free-running counter with 8-bit precision prescaler — 1 x 16-bit pulse accumulator • PIT (periodic interrupt timer) — Up to eight timers with independent time-out periods — Time-out periods selectable between 1 and 224 bus clock cycles — Time-out interrupt and peripheral triggers • 8 PWM (pulse-width modulator) channels — 8 channel x 8-bit or 4 channel x 16-bit Pulse Width Modulator — programmable period and duty cycle per channel — Center- or left-aligned outputs — Programmable clock select logic with a wide range of frequencies — Fast emergency shutdown input • Three Serial Peripheral Interface Modules (SPI) — Configurable for 8 or 16-bit data size • Eight Serial Communication Interfaces (SCI) — Standard mark/space non-return-to-zero (NRZ) format — Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths • Two Inter-IC bus (IIC) Modules — Multi-master operation — Software programmable for one of 256 different serial clock frequencies — Broadcast mode support — 10-bit address support • On-Chip Voltage Regulator — Two parallel, linear voltage regulators with bandgap reference — Low-voltage detect (LVD) with low-voltage interrupt (LVI) — Power-on reset (POR) circuit — 3.3V and 5V range operation — Low-voltage reset (LVR)
• Low-power wake-up timer (API) — Available in all modes including Full Stop Mode — Trimmable to +-5% accuracy — Time-out periods range from 0.2ms to ~13s with a 0.2ms resolution • Input/Output — Up to 152 general-purpose input/output (I/O) pins plus 2 input-only pins — Hysteresis and configurable pull up/pull down device on all input pins — Configurable drive strength on all output pins • Package Options — 208-pin MAPBGA — 144-pin low-profile quad flat-pack (LQFP) — 112-pin low-profile quad flat-pack (LQFP) — 80-pin quad flat-pack (QFP) • 50MHz maximum CPU bus frequency, 100MHz maximum XGATE bus frequency
Please make sure your contact information is correct. Your message will be sent directly to the recipient(s) and will not be publicly displayed. We will never distribute or sell your personal information to third parties without your express permission.