Features • Single issue, 32-bit CPU core complex (e200z0h) — Compliant with the Power Architecture® technology embedded category — Enhanced instruction set allowing variable length encoding (VLE) for code size footprint reduction. With the optional encoding of mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction. • Up to 1.5 MB on-chip code flash memory supported with the flash memory controller • 64 (4 × 16) KB on-chip data flash memory with ECC • Up to 96 KB on-chip SRAM • Memory protection unit (MPU) with 8 region descriptors and 32-byte region granularity on certain family members (Refer to Table 1 for details.) • Interrupt controller (INTC) capable of handling 204 selectable-priority interrupt sources • Frequency modulated phase-locked loop (FMPLL) • Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters • 16-channel eDMA controller with multiple transfer request sources using DMA multiplexer • Boot assist module (BAM) supports internal Flash programming via a serial link (CAN or SCI) • Timer supports I/O channels providing a range of 16-bit input capture, output compare, and pulse width modulation functions (eMIOS) • 2 analog-to-digital converters (ADC): one 10-bit and one 12-bit • Cross Trigger Unit to enable synchronization of ADC conversions with a timer event from the eMIOS or PIT • Up to 6 serial peripheral interface (DSPI) module
Up to 10 serial communication interface (LINFlex) modules • Up to 6 enhanced full CAN (FlexCAN) modules with configurable buffers • 1 inter-integrated circuit (I2C) interface module • Up to 149 configurable general purpose pins supporting input and output operations (package dependent) • Real-Time Counter (RTC) • Clock source from internal 128 kHz or 16 MHz oscillator supporting autonomous wakeup with 1 ms resolution with maximum timeout of 2 seconds • Optional support for RTC with clock source from external 32 kHz crystal oscillator, supporting wakeup with 1 sec resolution and maximum timeout of 1 hour • Up to 8 periodic interrupt timers (PIT) with 32-bit counter resolution • Nexus development interface (NDI) per IEEE-ISTO 5001-2003 Class Two Plus • Device/board boundary scan testing supported per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1) • On-chip voltage regulator (VREG) for regulation of input supply for all internal levels
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